The present invention relates to a magnetic recording and reproducing apparatus, and more particularly to a phase locked loop circuit for generating a reproducing clock to read and reproduce data from a recording medium or generating a write clock for recording data.
A magnetic recording and reproducing apparatus, as shown in FIG. 9, generally comprises a magnetic recording medium 101 such as a magnetic disk, a magnetic head 118, a read/write (R/W) amplifier 102, a read signal processing circuit 103, a write signal processing circuit 104, a controller 105, a microprocessor or microcomputer 106, a servo control unit 107 and an interface unit (I/F) 108.
The read and write signal processing circuits may be implemented in various ways. As an example, in a partial response maximum likelihood (PRML) system, the read signal processing circuit comprises an AGC circuit 111, an analog-to-digital (A/D) converter circuit 112, a partial response (PR) equalizer circuit 113, a Viterbi encoder circuit 115, a demodulator circuit 116 and a phase locked loop (PLL) circuit 901.
The recording and reproducing of data in the magnetic recording apparatus are explained.
Recording data sent from a host to record it in the magnetic recording and reproducing apparatus is sent to the write signal processing circuit 104 through the I/F 108 and the controller 105, encoded to a recording code which fits to the recording medium and then written into the recording medium 101 by driving the magnetic head 118.
The data read from the magnetic recording medium 101 by the magnetic head 118 and the R/W amplifier 102 is applied to the read signal processing circuit 103, adjusted to a proper signal amplitude by the AGC circuit 111, and then converted from the analog signal to a digital signal by the A/D converter circuit 112 and it is equalized to exhibit a characteristic of a partial response inter-code interference between classes by the PR equalizer circuit 113. Then, it is decoded by the Viterbi detector circuit 115 and decoded to the original data from the recording code by the decoder circuit 116. The decoded data is sent to the host through the controller 105 and the I/F 108.
The positioning of the magnetic head 118 and the rotation of the magnetic recording medium 101 are controlled by the servo control unit 107 and the microcomputer 106. In a data surface servo system, a portion of the read data forms servo data and a servo data signal alll is outputted from the read signal processing circuit 103 and it is used to control the positioning of the magnetic head 118.
The phase locked loop circuit 901 generates a sampling clock a106 of the A/D converter 112 and comprises a phase detection circuit 921, a digital-to-analog (D/A) converter circuit 922, a loop filter 923 and a voltage controlled oscillator (VCO) 924.
The phase detection circuit 921 detects a phase error of the sampling timing from the output signal a101 of the PR equalizer circuit 113 and outputs control data a902. The D/A converter circuit 922 outputs an analog current a903 corresponding to the digital control data a902, and it is integrated and filtered by a loop filter a923 to produce an input control voltage to the VCO 924. In this manner, the VCO 924 is controlled to synchronize the sampling clock a106.
The electronic circuits shown in FIG. 9 including the phase locked loop circuit 901 are integrated in one chip and the loop filter 923 is an off-chip element. A white circle (.smallcircle.) of the loop filter 923 represents off-chip pins. In FIG. 9, it indicates that one pin is required for the loop filter 923.
On the other hand, in the magnetic disk drive, a constant density recording system is primarily used to improve the recording capacity and means to modify the characteristic of the phase locked loop circuit 901 accordingly is required. In FIG. 9, the microcomputer 106 performs the control and produces control signals s101 and s102.
The constant density recording system is disclosed in JP-A-3-205920 (hereinafter referred to as a prior art reference 1) and IEEE 1993 CICC article "A 3-5.5V CMOS 32 Mb/s Fully Integrated Read Channel for Disk Drives (hereinafter referred to as a prior art reference 2).
In the prior art reference 1, a circuit for switching a loop filter 1003 of a phase locked loop circuit 901 as shown in FIG. 10 is used as the means to cope with the constant density recording system.
On the other hand, in the prior art reference 2, a loop 1105 is formed into a full differential type as shown in FIG. 11 and it is driven by four D/A converter circuits 1101 1104 (which may be charge pumping circuits in the peak detection type signal processing). Inputs to the VCO 1106 are differential inputs and connected to the opposite ends of the loop filter 1105. In this system, current gains of the D/A converter circuits 1101.about.1104 may be changed to control a loop gain and an attenuation factor of the phase locked loop circuit 901.
In the magnetic disk drive, the effort to increase a data transfer rate has been attempted for those years and the clock frequency has been increased to 100 MHz, for example. As a result, a specification to a timing margin is severe and the phase locked loop circuit has to suppress a clock jitter as much as possible. However, as the processing speed of the circuit increases, noises of a power supply and ground (GND) of a circuit board of the disk drive tend to increase more and more and this causes the increase of the clock jitter. Particularly, in a small size magnetic disk drive of less than 2.5 inches, since a power is supplied from the system and not from a regulated power supply, the noise immunity of the power supply line is weak and the low impedance of the circuit board wiring is not sufficient to cope therewith. Thus, countermeasure by the circuit configuration is needed.
As for the GND noise, a potential difference between GND in the IC and GND of the circuit board of the disk drive should be noticed. As described above, the electronic circuits are integrated and the respective circuits operate with reference to the GND potential of the IC. Where a noise is included in the GND of the circuit board of the disk drive, the noise may be introduced into the IC through the off-chip element connected to the GND of the circuit board.
It is therefore an important problem to reduce the logic jitter for the noises of the power supply and GND of the circuit board which are more and more becoming prominent as the transfer rate and the miniaturization of the disk drive are increased.
For the electronic circuit including the read signal processing circuit 103 and the write signal processing circuit 104, the user request to reduce the cost and the power consumption is strong. In order to attain it, it is an important problem to reduce the circuit scale of the respective circuits as much as possible to reduce the power consumption, enhance the integration and suppress the number of pins as small as possible to allow the use of an inexpensive IC package.
As to the constant density recording system, the following problem is also encountered.
In the prior art reference 1, as shown in FIG. 10, one end of the loop filter 1003 is connected to the GND. As a result, an AC potential difference between the GND and the reference potential in the VCO appears as a noise which is introduced into the input signal to the VCO to cause the clock jitter. Further, as the precision of the attenuation factor is increased, the number of the off-chip resistors required increases more and more and the number of pins increases.
On the other hand, in the prior art reference 2, as shown in FIG. 11, the loop filter 1105 is of full differential type which is resistive to the GND and power supply noises. However, in this prior art system, four D/A converter circuits are necessary and the circuit scale and the power consumption increase.